1. Field of the Invention
This invention relates to a semiconductor device and a manufacturing process thereof. In particular, it relates to a technique for connecting a gate electrode and a doped layer.
2. Description of the Related Art
A semiconductor device having a common contact for connecting both an electrode, such as gate electrode, and a doped layer has been conventionally formed as shown in the schematic sectional view of FIG. 11. Specifically, a gate electrode 204a consisting of polycrystalline silicon for forming a transistor via a gate oxide film 203a is formed on a surface of a silicon substrate 201 on which a device-isolation region 202 has been formed by a LOCOS or trench isolation technique, and spacers 205 consisting of silicon dioxide, are formed on the sides of the gate electrode 204a. On the substrate surface, a low-density doped layer 206 and a high-density doped layer 207(a,b) constituting an LDD transistor are formed in the region defined by the gate electrode 204a and the spacers 205. Atitanium silicide layer 208 for minimizing resistance is formed on the surfaces of the high-density doped layer 207 and the gate electrode 204. These constitute a N-type MOSFET (209). A wiring electrode 204b made of the same material as that of the gate electrode 204a is formed, via a gate oxide film 203b, on the silicon substrate 201 and the device-isolation region 202, for ensuring their electrical connection with the high-density doped layer 207b as a drain node for MOSFET (209). An interlayer insulating film 213 is formed on the wires and the transistor, and a common contact 214, in which a contact plug made of polysilicon or tungsten is buried, is formed, covering both the surface of the high-density doped layer 207b as a drain node and the electrode 204b. The common contact 214 is, if necessary, connected with wires in upper layers.
In this structure, the common contact 214 is electrically connected with the high-density doped layer 207b to be a drain node and the electrode 204b, covering a spacer 205. There has been, therefore, a problem that the size of the contact is reduced, the contact resistance increases. JP-A 4-63436 has disclosed an approach for solving this problem.
The approach is that the spacer 205, which has been formed on the portion to be connected with the common contact 214, is removed before forming the contact, to avoid an increase of the contact resistance by reduction of the contact size. The manufacturing process will be described with reference to the sectional process charts of FIGS. 12(a) to 12(e).
A gate electrode 204, consisting of polycrystalline silicon for forming a transistor via a gate oxide film 203, is formed on a surface of a silicon substrate 201 on which a device-isolation region 202 has been formed by a LOCOS or trench isolation technique. A low-density doped layer 206, constituting an LDD transistor is formed by, e.g., ion implantation. Then, spacers 205 consisting of silicon dioxide are formed on the sides of the gate electrodes 204 (FIG. 12(a)). On the substrate surface, high-density doped layers 207a, b are formed in the region defined by the gate electrodes 204 and the spacers 205 by ion implantation, and titanium silicide layers 208 for reduction of resistance are formed on the surfaces of the high-density doped layers 207 and the gate electrodes 204 (FIG. 12(b)). A resist 210 is. deposited on the substrate surface. After patterning, an opening 211 is formed for removing the spacer, which exists, in a portion where a contact plug is to be buried. Then, the spacer 205, exposed in the opening 211, is removed (FIG. 12(c)).
After removing the resist, an interlayer insulating layer 212, consisting of an oxide film and a BPSG film, is formed, and a common contact hole 213 is formed using a resist mask (FIG. 12(d)).
A barrier film 215 with a laminated structure of Ti and TiN is formed in the common contact hole 213 by, e.g., spattering, and then a metal material 216, such as tungsten, is buried to form a common contact 214 (FIG. 12(e)).
In the prior art, shown in FIG. 12e, there has been, however, a problem that since the barrier film 215 is formed on the low-density doped layer 206, current leak may occur between the common contact 214 and the substrate 201.
To avoid the current leak, it is necessary to conduct some procedure such as implanting an impurity of the same conduction type as that of the high-density doped layer 207 after forming the contact hole 213. Specifically, for achieving a CMOS structure, there should be added two lithography steps, i.e., one for an NMOS and one for a PMOS.
Further, when a contact is formed in a region where silicon is exposed, the resistance becomes about ten times that for a device having an aspect ratio of about 3 of the contact, even if an impurity is introduced with high density. This may be mainly due to the fact that a barrier film having an adequate thickness cannot be formed by spattering on the bottom of the contact having a large aspect ratio In addition, inadequate treatment of the silicon surface may easily lead to increasing the resistance by a couple orders og magnitude.
Since an adequately low contact resistance cannot be obtained in this portion, an offset of the common contact should be strictly controlled. Specifically, for connecting the common contact with both the doped layer and the gate electrode, an offset of R/2 for one side maybe ideally allowed, where R is the contact diameter. In the structure of the prior art, forming a spacer having a width W on a side wall of the gate may lead to decreasing the allowed width to (R-W)/2. The smaller R is, the more remarkable the influence is.
An object of this invention is to provide a technique for connecting a gate electrode with a doped layer without current leak, with a reduced number of manufacturing steps, for solving the above problems.
This invention provides a semiconductor device comprising a gate insulating film formed on a main surface of a silicon substrate having a device-isolation region, a gate electrode consisting of polycrystalline silicon, spacers for forming an LDD-MOSFET on the sides of the gate electrode, and a high-density doped layer, characterized in that the spacer which has been formed on the side wall of the gate near to and connected with the high-density doped layer, is removed at least before forming the high-density doped layer, and the gate electrode is electrically connected with the high-density doped layer via a metal silicide formed on the high-density doped layer after removing the spacer.
This invention also provides a process for manufacturing a semiconductor device comprising at least.
(1) forming a device-isolation region on a main surface of a silicon substrate,
(2) forming a gate insulating film,
(3) forming a gate electrode,
(4) forming a spacer on a side wall of the gate electrode for manufacturing a LDD-MOSFET,
(5) removing a part of the spacer on the side wall,
(6) forming a high-density doped layer in a region defined by the device-isolation region and the gate electrode, and
(7) forming a metal silicide layer over at least all the exposed surface of the high-density doped layer,
characterized in that the side of the gate electrode on which the side wall spacer has been removed is electrically connected with the high-density doped layer via the metal silicide layer deposited in the above step (7).
In the semiconductor device and the manufacturing process therefore of this invention, a gate electrode can be automatically connected with a doped layer in a silicide step only by partially removing a spacer on the side wall of the gate electrode, leading to a minimal increase, in steps for connection. It should be noted that since all the lower surface of the silicide layer is covered with a high-density doped layer, current leak could be avoided without ion implantation after forming a contact.
Furthermore, when the silicide layer cannot be formed on the side wall of the gate electrode due to manufacturing conditions etc., a common contact hole can be formed in the portion, and the gate electrode may be electrically connected with the high-density doped layer via an implanted contact plug and on the substrate corresponding to the bottom of the contact hole there is a high-density doped layer, leading to no current leak to the substrate.
Furthermore, for an SRAM, where an extremely fine doped layer should be formed, even when the opening area for removing the side wall spacer is overlapping a part of the device-isolation region, etching of an insulating film buried in the device-isolation region may be avoided by forming the side wall spacer constituting the LDD-MOSFET as a laminated structure of an oxide film/a nitride film/an oxide film or an oxide film/a nitride film to utilize the formed nitride film as an etching stopper while removing the oxide film(s).